B-Tech: Undergraduate

Title – Design and Implementation of UNIVERSAL ASYNCHRONOUS RECEIVER TRANSMITTER(UART)PROTOCOL .

Guide – Prof. Narinder Singh, VLSI Lab, Department of  Instrumentation and Control Engg., National Institute of Technology, Jalandhar

Duration – Academic year 2008-2009

Aim and Scope – The thesis aims to study the design, modelling, simulation and implementation of UART Protocol. Simulation studies are done on Model-Sim, Xilinx and real time implementation is done on FPGA Spartan Kit.Coding is done with VHDL and VERILOG.As FPGA based processors are fast as compared to traditional processors.After implementation of this project, the speed of data processing, memory usage, power consumption are optimized and promising results are reflected in the simulation of prototype design.

Status - Completed

M-Tech: Graduate

Title – Multiprogramming models of  Unit Commitment optimization using Matlab/C

Guide- Prof. Ashutosh,Power System Planning Lab, Department of  Electrical Engg.,School of Electrical and Electronics Engg. , Lovely Professional University

Duration – Academic year 2012-2013

Aim and Scope – The thesis aims to study the Design, Modelling, Simulation of mathematical algorithms used for the optimal scheduling of Unit Commitment Problem. Simulation study includes Dynamic programming approach, Langrangean multipliers,Enumeration,priority lisiting,linear programming,integer,mixed integer programming,Tabu search,Neural Network,Genetic algorithms.The algorithms are implemented in Matlab/Simulink/C. Results will be compared for specific standard set of dynamics.

Status – In Progress